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CURRICULUM VITAEPRIVATE
PERSONAL
Nationality:
BRITISH
Security:
previously cleared
EDUCATION
MSc
Advanced
Microelectronics for Industrialists (2004, Bolton Institute, UK)
PROFILE - SKILLS – HW – SW - APPLICATIONS
– CAE – ASIC’s - FPGA’s – Operating Systems
Profile:
Lots
of years of experience in Electronics Design and Development of
which last few years have been in IC, ASIC/FPGA
design/development, vhdl, verilog, synthesis, simulation and
verification in Semiconductors, Telecommunications, Defence and
Aerospace/Avionics industries.
Skill:
IC, ASIC/FPGA Design/Development & Verification, System
Integration, System Engineering
Hardware:
IC, ASIC, FPGA, Digital, DSP, ARM, Analogue, Optics, Micro
[snip] 32 bits, Micro Intel 8, 16 bits
Software:
VHDL, Verilog, C, Assembler, Shell
scripts
Applications:
Set Top Box (STB), Multimedia Mobile Phone, Chipcard, Flash
Memory, Aerospace (HUD), Wireless (UMTS-
WCDMA/GSM), Wireless Access (Bluetooth), Wireless LAN, Telecomm,
ATM/Utopia, ADSL, LAN, SDH, WDM, GSM, BSC, EMC/EMI
CAE:
Cadence suite of tools, Mentor Graphics suite of tools, Synopsys
DC, Modelsim, LeonardoSpectrum
Programmable
ASIC’s – PLD’s/FPGA’s:
Xilinx, Altera, Lucent, and Cypress
Semi-custom –
ASIC’s:
ST(0.09u), [snip](0.065u,0.09u), Infineon(0.11u), Mitel Asics
GSC400 (0.18u)
OS:
UNIX/LINUX, Windows
CAREERS HISTORY
[snip] From: Dec 06- July
07 Position: FPGA Design Engineer
Essex
Design
and verification of an FPGA for a fault-tolerant control system,
that requires safety critical shutdown for the automation
industry.
Determine functional requirements and produce a design
description for the 10/100 Base-T Ethernet RMII Interface,
Serial SPI Flash interface, HDLC/NRZI and UART blocks within the
device.
Determine general structure and interconnection of the blocks
Implement design in RTL VHDL
Write design functional verification tests in behavioural VHDL.
Perform simulation
Interfaces:
Ethernet RMII Interface, Serial SPI Flash interface, HDLC, NRZI,
UART
Hardware:
Lattice LFE2-12E-5F256l device
CAE:
Synplify for synthesis, Modelsim for simulation,
Lattice
ISP place and route suite of tools used for optimisation to the
target FPGA.
OS/Software:
Windows XP, VHDL
[snip] From: Oct 05-Oct 06 Position:
ICIntegration/ Verification Engineer
Avon
Integration of
baseband IP’s into a large Set Top Box (stb) IC.
Integration of IP’s transport, video, audio,
graphics.
Interfaces:
DDR SDRAM, USB 2.0, modem, serial ATA, Flash, Main/Aux video
Hardware:
ST240, ST30 (audio+video decode), STbus, transport filtering &
descrambling, video decode H.264/AVC
MPEG-4 & MPEG-2, graphics engine, audio decode.
CAE:
SUN
workstations under UNIX, Cadence NC-Sim for simulation
Software:
VHDL
[snip] From: May 05-Sep 05 Position:
ICIntegration/Verification Engineer
Netherlands
Integration of baseband
IP’s into a large multimedia IC for the next generation of
mobile phones.
Integration of IP’s Control DAC, 10-bit DAC via buses AXI/AHB to
APB/VPB.
Investigation on use of chiplet synthesis, .sdc files and LEDA
screener in order to use
Cadence RTL compiler for synthesis.
Interfaces:
AXI, AHB, APB, VPB
Hardware:
Arm1176, Amba bus, Axi bus,
CAE:
HP
workstations under UNIX used to run Cadence suite of tools,
Cadence NC-Sim for simulation
Software:
VHDL, VERILOG, TCL, CVS
[snip] From: Sep 04-Feb 05 Position: IC
Design/Verification Engineer
Austria
Design & Verification of a
Security Chipcard Controller based on Microcontroller
architecture. Implement Reset and System (sleep/wakeup) blocks
within the device.
Implement design in RTL VHDL.
Write new design functional verification testcases in asm for
pre-silicon verification.
Add new testcases to the existing regression testcases, debug
and verify the device for rtl,
gate-level, ipo and routed phases.
Interfaces:
Reset, System Hardware: Microcontroller
CAE:
SUN
workstations under UNIX used to run Cadence suite of tools,
Cadence NC-Sim for simulation
Software:
asm, VHDL, VERILOG, Clearcase
[snip] From: Sep 03-June 04
Position: IC/Verilog Design Engineer
Germany
Design and verification of the next phase
of 2G Bit Nand Flash Memory that is targeted to (0.11u) series
technology. Digital part of mixed signal Integrated Circuit
(IC).
Determine functional requirements and produce an implementation
specification for Powerbit and Address Buffer blocks within the
device,
Determine general structure and interconnection of the blocks
Implement design in RTL VERILOG
Write design functional verification tests for the
blocks and later on the system in behavioural VERILOG.
Perform simulation
HDL code Coverage using HAL, and assertion checks
for increased verification.
Interfaces:
Array Databus, user io Hardware: IC (0.11u)
CAE:
SUN
workstations under UNIX used to run Cadence suite of tools,
Cadence NC-Sim for simulation
Software:
VERILOG - link:
[snip] From: Jul 01- Jan
02 Position: VHDL Design Engineer
Kent
Involved in design and verification of a CPLD
device. It forms part of equipment called Display Drive Unit (DDU).
The DDU forms part of the overall equipment called Head-Up
Display (HUD) unit.
Determine
functional requirements and produce a Hardware Requirement
Specification.
Determine
design architecture, including chip I/O pads and produce
Implementation Specification.
Determine general structure and
interconnection of major blocks. Implement design in RTL VHDL.
Write
design functional verification tests in behavioural VHDL.
Perform simulation
Interfaces:
Texas TMS320C32, External memory i/f, HDLC i/f, I2C i/f,
ARINC i/f
Hardware:
Cypress 37512, 512 macrocell device
CAE:
Leanardo Spectrum for synthesis, Modelsim for simulation,
TimingDesigner for timing analysis,
Cypress place and route suite of tools used for optimisation to
the target CPLD.
OS/Software:
Windows NT, VHDL - link:
[snip] From: May 01-Jul
01 Position: LSI Design Engineer Berks
Design and
development of a `GSM baseband Reference Platform` hardware
development system, that includes a prototype board containing
an FPGA, which will enable current UMTS-WCDMA only mode mobile
phone to be used in both UMTS-WCDMA and GSM dual band mode.
Select
appropriate CAE and FPGA vendors for the current project.
Interfaces:
Serial uplink/downlink Interface, ARM7 bus i/f, DSP bus i/f
Hardware:
Altera 300K gate device EP20K300E
CAE:
Mentor Design Architect for schematic capture, Quartus II
OS:
Windows NT, Verilog
[snip].,
From: Nov 99-Apr 01 Position: ASIC/Verilog Design
Engineer Lincolnshire
Involved in design and verification of the
next phase of digital Bluetooth Radio Interface module
based on BlueRF specification supporting RXMODE2 and
Bi-directional mode that is targeted to
GSC400 (0.18u) series.
Digital part of System On Chip (Soc) mixed signal asic.
Determine
functional requirements and produce an implementation
specification.
Determine
design architecture, including chip I/O pads
Determine general structure and
interconnection of major blocks
Determine design for low power, using gated
clocks
Implement design in RTL VERILOG
Write
design functional verification tests in behavioural VERILOG.
Perform simulation
Synthesise
design. Analyse synthesis output, set optimisation constraints.
Perform gate-level simulation.
Perform static timing analysis (STA) using
Primetime
Back-annotate timing information from layout into simulator and
synthesis tools.
Perform
internal scan insertion; Implement boundary scan (JTAG).
Implemented DFT backend processes that
determine tester pattern methodology and develop tester patterns
on a Global Positioning System (GPS).
Modified testbenches for different blocks
within the system in verilog, followed by the system itself
which was in vhdl to take the product through production,
targeted to Mitel’s CLA200 ASIC device
Test Pattern Generation (TPG). Test Pattern
Verification (TPV).
Fault Coverage using Verifault, then
Powerfault performing iddq tests to increase overall fault
coverage.
Earlier
designed a prototype, which was a precursor to the above design.
A digital
control interface between the Baseband Interface and other
blocks of a Bluetooth.
The prototype design was targeted towards Xilinx Virtex series.
Design flow similar to above
Interfaces:
Serial Interface, ARM7 processor (embedded), SCAN, JTAG
Hardware:
Mitel Asics CLA200 (0.35u), GSC400 (0.18u) and Xilinx Virtex
XCV400
CAE:
SUN
workstations under UNIX used to run Cadence suite of tools,
Verilog-XL for simulation
Synopsys Design Compiler for synthesis and Primetime for STA
Software:
VERILOG - link: , VHDL -, C/C++, Shell scripts
[snip], From: Feb 98 - July
99 Position: VHDL Design Engineer Cambridge
Designed 2
Utopia II Slave Interfaces (UTSlv) running at 50 MHz between an
ATM switch fabric and upto 30 ADSL line-card channels. Produced
functional requirement specifications for Line Card Interface.
Determine design requirements, partitioning,
general structure, interconnection of major blocks, chip I/Os.
Implement design in RTL VHDL, write
functional verification tests in behaviour VHDL. Perform
simulation. Synthesise design, analyse synthesis output, set
optimisation constraints, determine timing critical paths.
Back-annotate
timing information from the vendor tool into simulator and
synthesis tools
The
FPGA’s were tested on the card and the shelf to fully verify the
design functionality
Interfaces:
ATM /Utopia II Master’s, ADSL Line Cards
Hardware:
Two ORCA2 FPGA’s 20K each, 80 % full, Two ORCA 3 series FPGA’s
80K each, 95% full
CAE:
Renoir for hierarchical block diagrams, Modelsim for simulation,
Synopsys Design Compiler for synthesis
Lucent ORCA place and route suite of tools used for optimisation
to the target FPGA.
OS/Software:
Windows NT used to run HdlAuthor for VHDL text based entry
[snip], From: Sep 97 - Dec 97 Position:
VHDL Development Engineer Beds.
Development of
a Gigabit Interface Loopback Module (GILM) to be used in a LAN
in which up to 120 Bridge Units (BU), each consisting of 3
ports; may be connected via Fibre Optic cables in any topology
within the network. Identify the lowest BU within the network
that will be the master and will send a token to all other BU’s
in order to produce a single data loop within the network
Determine
general structure and interconnection of major blocks
Implement
design in RTL VHDL, write functional verification tests in
behaviour VHDL. Perform simulation.
Hardware:
Altera 7000 series FPGA
CAE:
Modelsim for simulation. Altera for synthesis, place and
route tools used for optimisation to the target FPGA.
OS/Software:
Windows NT used to run Turbowriter for VHDL text based entry
[snip] From: Sep 96 – Aug 97
Position: VHDL Design Engineer London
Designed an
FPGA that controls and monitors an ASIC, processes Overhead
Processor Unit (OPU) data and is controlled and monitored by
Alarm Interface FPGA. It is used on Encoder and Decoder cards of
SDH WDM Terminal of a 2.5 Gigahertz SLTE equipment. Produced
functional requirement specifications for the FPGA.
Determine design requirements, partitioning,
general structure, interconnection of major blocks, chip I/Os.
Implement design in RTL VHDL, write
functional verification tests in behaviour VHDL. Perform
simulation. Synthesise design, analyse synthesis output, set
optimisation constraints, determine timing critical paths.
Back-annotate
timing information from the vendor tool into simulator and
synthesis tools
The
FPGA was tested on the card and the shelf to fully verify the
design functionality
Interfaces:
Intel 8088 type Interface, Processor type interface, OPU
Interface
Hardware:
Xilinx 4000e series FPGA of 10K density
CAE:
EASE for hierarchical block diagrams, Modelsim used for
simulation, Leonardo for synthesis. Xilinx place and
route suite of tools used for Optimisation to the target FPGA.
OS/Software:
Windows NT used to run Turbowriter for VHDL text based entry
[snip],
Cambridge From: Jan 96-Sep 96 Position: ASIC
Design Engineer
Design and verification of sub-blocks within APOC ASIC Paging
Decoder.
Determine design requirements, partitioning,
general structure, interconnection of major blocks, chip I/Os.
Synthesise design, Analyse
synthesis output, set optimisation constraints,
Perform gate-level
simulation.
Hardware:
[snip] 0.5u ASIC
CAE:
Synergy/Verilog for Verilog synthesis, Compass for circuit
schematics
OS:
SUN workstations under UNIX used to run Cadence suite of tools
[snip] From: April 95 - Dec
95 Position: ASIC Design Engineer Hampshire
Development/verification of a Parity Watchdog ASIC utilised in
the M68020 based processor card of an Electronic Engine
Controller System employed within a BR710 Engine.
Implement design in RTL VHDL and Schematics,
Write design functional verification tests in MISL.
Perform simulation and Synthesise
design, Analyse synthesis output, set optimisation constraints
Hardware:
[snip] H4C Series ASIC,
CAE:
Design Architect for schematic capture, Quicksim2 for
simulation, Autologic for VHDL synthesis.
[snip] tools for Optimisation to the target ASIC
OS:
SUN workstations under UNIX used to run Mentor Graphics version
8.4 suite of tools
[snip]
-Swindon, Wiltshire From: Jan 95 - April 95
Position: Hardware Development Engineer
Development of
a Fibre Optic Multiplexer card used in the New Generation Base
Station System (BSS) of a GSM system which multiplexing/demultiplexing
of upto 24 2MHz carriers.
Verification of
design, Investigate design flaws, Optimisation. Produce Test
Specification for the module.
Hardware:
Altera 8820 FPGA, ECL, FAST, and FCT
CAE:
Design Architect for schematic capture, Quicksim2 for
simulation, Autologic for VHDL synthesis.
Altera tools for Optimisation to the target FPGA
OS/Software:
HP workstations under HP-UNIX used to run Mentor Graphics
version 8.4 suite of tools. VHDL.
[snip] From: Jan 77 – Nov 94
Position: Team Leader
UK
Position:
Hardware Design Engineer
Design of
special‑to‑type test equipment and to produce Acceptance
Specification to verify a Line Replacement Unit used on
Electronic Counter Measures (ECM) system. Processor card
containing a [snip] 68020 microprocessor, SCC, CIO, BOOTPROM,
EEPROM, SRAM, FIFO's, DMA control circuit and PAL glue logic.
Design of
Hand‑held (Palmtop PC) programmer to enable the user to program,
monitor and edit Programmable Logic Controllers (PLC).
Programmer is based on Intel 8088 microprocessor, RS232 Serial
interface, current loop interface, AudioTape interface and LCD
display for automated high volume production.
Design of
digital, analogue and optics for a system used to measure
attenuation.
Responsible for
data processing sub‑system based on Intel 80186 microprocessor
to meet the processing requirement. Interface via Intel multibus,
or local bus protocol used on Sonar Systems. Multibus, A/D, D/A,
and DSC.
In AEW Mission
Simulator Group, designed a sub‑system for multiple Minicomputer
systems to access one set of peripherals. If another system
requires access, then an interrupt routine was generated to
select the appropriate system.
Within the
Instrumentation group of the Air Intercept Tornado Aircraft,
designed a special‑to‑type interface between the industrial
Video Tape Recorder and the Control Panel Interface Unit, using
Miller encode/decode technique. Designed test equipment to
simulate Mission Systems Recorder in order that known target
pulses are generated and then verified on Tape Analysis
equipment. |
